[1]高梓喻,蒋永吉,李曼,等.薄硅膜金属-绝缘层-半导体结构的电容-电压特性[J].应用科技,2017,44(01):40-44.[doi:10.11991/yykj.201609004]
 GAO Ziyu,JIANG Yongji,LI Man,et al.Capacitance-voltage characteristics of the metal-insulator-semiconductor structure with thin silicon film[J].Applied science and technology,2017,44(01):40-44.[doi:10.11991/yykj.201609004]
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《应用科技》[ISSN:1009-671X/CN:23-1191/U]

卷:
第44卷
期数:
2017年01期
页码:
40-44
栏目:
现代电子技术
出版日期:
2017-02-05

文章信息/Info

Title:
Capacitance-voltage characteristics of the metal-insulator-semiconductor structure with thin silicon film
作者:
高梓喻12 蒋永吉12 李曼12 郭宇锋12 杨可萌12 张珺12
1. 南京邮电大学 电子科学与工程学院, 江苏 南京 210003;
2. 射频集成与微组装技术国家与地方联合工程实验室, 江苏 南京 210003
Author(s):
GAO Ziyu12 JIANG Yongji12 LI Man12 GUO Yufeng12 YANG Kemeng12 ZHANG Jun12
1. College of Electronic Science and Engineering, Nanjing University of Posts and Telecommunications, Nanjing 210003, China;
2. National & Local Joint Engineering Laboratory for RF Integration and Micro-packaging Technologies, Nanjing 210003, China
关键词:
硅膜厚度MIS结构电容-电压特性绝缘层固定电荷
Keywords:
thickness of silicon filmMIS structurecapacitance-voltage characteristicsfixed insulator charge
分类号:
TN386
DOI:
10.11991/yykj.201609004
文献标志码:
A
摘要:
随着各种新纳米CMOS器件技术的出现,在等比例缩小原则的限制下,硅膜厚度逐渐减薄,这对通过电容-电压法进行物理参数提取带来了挑战。本文借助半导体二维仿真器件——MEDICI,研究了不同硅膜厚度下金属-绝缘层-半导体结构的低频和高频电容-电压特性,通过研究不同偏置下的能带结构探讨了其内在物理机理,并分析了考虑金属与半导体功函数差、绝缘层固定电荷等因素的影响时该结构的电容-电压特性,为通过电容-电压特性法对薄硅膜MIS结构进行参数提取与表征进行了有益探索。
Abstract:
With the emergence of various new nano CMOS device technologies, the thickness of silicon film is gradually thinning under the restriction of the principle of scaling down, it is a challenge to extract physical parameters by capacitance-voltage method. By using the two-dimensional simulator MEDICI, low-frequency and high-frequency capacitance-voltage characteristics of the metal-insulator-semiconductor structure under different silicon film thickness were investigated in this paper. The inherent physical mechanism was researched by band structures under different bias, in addition, by considering the influence of the work function difference between the metal and semiconductor, fixed insulator charges and so on, the capacitance-voltage characteristics of this structure were analyzed. This work contributes to the parameter extraction and characterization of MIS transistor with thin silicon film.

参考文献/References:

[1] SHEU B, OLSTEIN K. Moore’s law challenges below 10nm:technology, design, and economic implications[J]. IEEE solid-state circuits magazine, 2015, 7(2):67-68.
[2] ESTIVILL R, GRENIER A, PRINTEMPS T, et al. 3D atomic scale analysis of CMOS type structures for 14 nm UTBB-SOI technology[J]. Microscopy and microanalysis, 2015, 21(S3):521-522.
[3] BARDON M G, SCHUDDINCK P, RAGHAVAN P, et al. Dimensioning for power and performance under 10nm:the limits of FinFETs scaling[C]//Proceedings of the 2015 International Conference on IC Design & Technology. Leuven, Belgium:IEEE, 2015:1-4.
[4] PAZ B C, ÁVILA-HERRERA F, CERDEIRA A, et al. Double-gate junctionless transistor model including short-channel effects[J]. Semiconductor science and technology, 2015, 30(5):1-11.
[5] TRIVEDI V P, FOSSUM J G. Nanoscale FD/SOI CMOS:thick or thin box[J]. IEEE electron device letters, 2005, 26(1):26-28.
[6] GNANI E, GNUDI A, REGGIANI S, et al. Physical model of the junctionless UTB SOI-FET[J]. IEEE transactions on electron devices, 2012, 59(4):941-948.
[7] YU Xiao, KANG Jian, TAKENAKA M, et al. Experimental study on carrier transport properties in extremely-thin body Ge-on-insulator (GOI) p-MOSFETs with GOI thickness down to 2 nm[C]//Proceedings of the IEEE International Electron Devices Meeting. Washington, DC:IEEE, 2015:2.2.1-2.2.4.
[8] LEE Y J, CHO T C, KAO K H, et al. A novel junctionless FinFET structure with sub-5nm shell doping profile by molecular monolayer doping and microwave annealing[C]//Proceedings of the 2014 IEEE International Electron Devices Meeting. San Francisco, CA, USA:IEEE, 2014:32.7.1-32.7.4.
[9] SRIVASTAVA V M. Capacitance-voltage measurement for characterization of a metal-gate MOS process[J]. International journal of recent trends in engineering, 2009, 1(4):4-7.
[10] SZE S M, NG K K. Physics of semiconductor devices[M]. New York:Wiley, 2015:197-240.

备注/Memo

备注/Memo:
收稿日期:2016-09-05。
基金项目:国家自然科学基金项目(61574081);教育部博士点基金项目(20133223110003);江苏省自然科学基金项目(BK20130778);江苏省工业支撑计划项目(BE2013130);国家重点实验室基金项目(KFJJ201403).
作者简介:高梓喻(1994-),男,大学本科;郭宇锋(1974-),男,教授,博士生导师,博士.
通讯作者:郭宇锋,E-mail:yfguo@njupt.edu.cn.
更新日期/Last Update: 2017-02-10